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Load-Acquire RCpc Register Halfword.


LDAPRH Wt, [Xn|SP {,#0}]


Is the 32-bit name of the general-purpose register to be loaded.
Is the 64-bit name of the general-purpose base register or stack pointer.

Architectures supported

This instruction is supported in architectures ARMv8.3-A and later. It is optionally supported in ARMv8.2-A with the RCpc extension.


Load-Acquire RCpc Register Halfword derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Store-Release in the ARMv8-A Architecture Reference Manual, except that:

  • There is no ordering requirement, separate from the requirements of a Load-Acquirepc or a Store-Release, created by having a Store-Release followed by a Load-Acquirepc instruction.
  • The reading of a value written by a Store-Release by a Load-Acquirepc instruction by the same observer does not make the write of the Store-Release globally observed.

This difference in memory ordering is not described in the pseudocode.

For information about memory accesses, see Load/Store addressing modes in the ARMv8-A Architecture Reference Manual.