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Store-Release Register.


This instruction is supported only in ARMv8.


STL{cond} Rt, [Rn]

STLB{cond} Rt, [Rn]

STLH{cond} Rt, [Rn]


is an optional condition code.
is the register to store.
is the register on which the memory address is based.


STL stores data to memory. If any loads or stores appear before a store-release in program order, then all observers are guaranteed to observe the loads and stores before observing the store-release. Loads and stores appearing after a store-release are unaffected.

If a store-release follows a load-acquire, each observer is guaranteed to observe them in program order.

There is no requirement that a store-release be paired with a load-acquire.

All store-release operations are multi-copy atomic, meaning that in a multiprocessing system, if one observer observes a write to memory because of a store-release operation, then all observers observe it. Also, all observers observe all such writes to the same location in the same order.


The address specified must be naturally aligned, or an alignment fault is generated.

The PC must not be used for Rt or Rn.


This 32-bit instruction is available in A32 and T32.

There is no 16-bit version of this instruction.