Signed saturating parallel byte-wise addition.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction performs four signed integer additions on
the corresponding bytes of the operands and writes the results into
the corresponding bytes of the destination. It saturates the results
to the signed range -27 ≤
27 -1. The Q flag is not affected even
if this operation saturates.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GE flags.
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.