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Literal pools

The assembler uses literal pools to store some constant data in code sections. You can use the LTORG directive to ensure a literal pool is within range.

The assembler places a literal pool at the end of each section. The end of a section is defined either by the END directive at the end of the assembly or by the AREA directive at the start of the following section. The END directive at the end of an included file does not signal the end of a section.

In large sections the default literal pool can be out of range of one or more LDR instructions. The offset from the PC to the constant must be:

  • Less than 4KB in ARM or Thumb code when the 32-bit LDR instruction is available, but can be in either direction.
  • Forward and less than 1KB when only the 16-bit Thumb LDR instruction is available.

When an LDR Rd,=const pseudo-instruction requires the immediate value to be placed in a literal pool, the assembler:

  • Checks if the value is available and addressable in any previous literal pools. If so, it addresses the existing constant.
  • Attempts to place the value in the next literal pool if it is not already available.

If the next literal pool is out of range, the assembler generates an error message. In this case you must use the LTORG directive to place an additional literal pool in the code. Place the LTORG directive after the failed LDR pseudo-instruction, and within the valid range for an LDR instruction.

You must place literal pools where the processor does not attempt to execute them as instructions. Place them after unconditional branch instructions, or after the return instruction at the end of a subroutine.

Example of placing literal pools

The following example shows the placement of literal pools. The instructions listed as comments are the ARM instructions generated by the assembler.

        AREA     Loadcon, CODE, READONLY
        ENTRY                      ; Mark first instruction to execute
        BL       func1             ; Branch to first subroutine
        BL       func2             ; Branch to second subroutine
        MOV      r0, #0x18         ; angel_SWIreason_ReportException
        LDR      r1, =0x20026      ; ADP_Stopped_ApplicationExit
        SVC      #0x123456         ; ARM semihosting (formerly SWI)
        LDR      r0, =42           ; => MOV R0, #42
        LDR      r1, =0x55555555   ; => LDR R1, [PC, #offset to
                                   ; Literal Pool 1]
        LDR      r2, =0xFFFFFFFF   ; => MVN R2, #0
        BX       lr
        LTORG                      ; Literal Pool 1 contains
                                   ; literal Ox55555555
        LDR      r3, =0x55555555   ; => LDR R3, [PC, #offset to
                                   ; Literal Pool 1]
        ; LDR r4, =0x66666666      ; If this is uncommented it
                                   ; fails, because Literal Pool 2
                                   ; is out of reach
        BX       lr
        SPACE    4200              ; Starting at the current location,
                                   ; clears a 4200 byte area of memory
                                   ; to zero
        END                        ; Literal Pool 2 is inserted here, 
                                   ; but is out of range of the LDR
                                   ; pseudo-instruction that needs it