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Test bits.


TST{cond} Rn, Operand2



is an optional condition code.


is the ARM register holding the first operand.


is a flexible second operand.


This instruction tests the value in a register against Operand2. It updates the condition flags on the result, but does not place the result in any register.

The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as an ANDS instruction, except that the result is discarded.

Register restrictions

In this Thumb instruction, you cannot use SP or PC for Rn or Operand2.

In this ARM instruction, use of SP or PC is deprecated in ARMv6T2 and above.

For ARM instructions:

  • If you use PC (R15) as Rn, the value used is the address of the instruction plus 8.

  • You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

Condition flags

This instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following form of the TST instruction is available in Thumb code, and is a 16-bit instruction:

TST Rn, Rm

Rn and Rm must both be Lo registers.


This ARM instruction is available in all architectures that support the ARM instruction set.

The TST Thumb instruction is available in all architectures that support the Thumb instruction set.


    TST     r0, #0x3F8
    TSTNE   r1, r5, ASR r1