Signed parallel subtract and add halfwords with exchange.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction exchanges the two halfwords of the second operand, then performs a subtraction on the two top halfwords of the operands and an addition on the bottom two halfwords. It writes the results into the corresponding halfwords of the destination. The results are modulo 216. It sets the APSR GE flags.
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
This instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
for bits[15:0] of the result.
for bits[31:16] of the result.
It sets a pair of GE flags to 1 to indicate that the corresponding result is greater than or
equal to zero. This is equivalent to an
instruction setting the N and V condition flags to the same value, so that the GE condition
You can use these flags to control a following
GE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.