Dual 16-bit Signed Multiply with Addition of products, and optional exchange of operand halves.
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
is an optional condition code.
is the destination register.
are the registers holding the operands.
SMUAD multiplies the bottom halfword
with the bottom halfword of
and the top halfword of
the top halfword of
. It then
adds the products and stores the sum to
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
SMUAD instruction sets the
Q flag if the addition overflows.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
SMUAD r2, r3, r2