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Signed Multiply Accumulate, with 16-bit operands and a 32-bit result and accumulator.


SMLA<x><y>{cond} Rd, Rn, Rm, Ra



is either B or T. B means use the bottom half (bits [15:0]) of Rn, T means use the top half (bits [31:16]) of Rn.


is either B or T. B means use the bottom half (bits [15:0]) of Rm, T means use the top half (bits [31:16]) of Rm.


is an optional condition code.


is the destination register.

Rn, Rm

are the registers holding the values to be multiplied.


is the register holding the value to be added.


SMLAxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, adds the 32-bit result to the 32-bit value in Ra, and places the result in Rd.

Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

This instruction does not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, SMLAxy sets the Q flag. To read the state of the Q flag, use an MRS instruction.


SMLAxy never clears the Q flag. To clear the Q flag, use an MSR instruction.


This ARM instruction is available in ARMv6 and above, and E variants of ARMv5T.

This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.

There is no 16-bit version of this instruction in Thumb.


    SMLABBNE    r0, r2, r1, r10
    SMLABT      r0, r0, r3, r5