You copied the Doc URL to your clipboard.


Logical OR.


ORR{S}{cond} Rd, Rn, Operand2



is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.


is an optional condition code.


is the destination register.


is the register holding the first operand.


is a flexible second operand.


The ORR instruction performs bitwise OR operations on the values in Rn and Operand2.

In certain circumstances, the assembler can substitute ORN for ORR, or ORR for ORN. Be aware of this when reading disassembly listings.

Use of PC in 32-bit Thumb instructions

You cannot use PC (R15) for Rd or any operand with the ORR instruction.

Use of PC and SP in ARM instructions

You can use PC and SP with the ORR instruction but this is deprecated in ARMv6T2 and above.

If you use PC as Rn, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

Condition flags

If S is specified, the ORR instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following forms of the ORR instruction are available in Thumb code, and are 16-bit instructions:

ORRS Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used outside an IT block.

ORR{cond} Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

It does not matter if you specify ORR{S} Rd, Rm, Rd. The instruction is the same.


    ORREQ   r2,r0,r5