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Load Register Exclusive.


LDREX{cond} Rt, [Rn {, #offset}]

LDREXB{cond} Rt, [Rn]

LDREXH{cond} Rt, [Rn]

LDREXD{cond} Rt, Rt2, [Rn]



is an optional condition code.


is the register to load.


is the second register for doubleword loads.


is the register on which the memory address is based.


is an optional offset applied to the value in Rn. offset is permitted only in 32-bit Thumb instructions. If offset is omitted, an offset of zero is assumed.


LDREX loads data from memory.

  • If the physical address has the Shared TLB attribute, LDREX tags the physical address as exclusive access for the current processor, and clears any exclusive access tag for this processor for any other physical address.

  • Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.

LDREXB and LDREXH zero extend the value loaded.


PC must not be used for any of Rt, Rt2, or Rn.

For ARM instructions:

  • SP can be used but use of SP for Rt or Rt2 is deprecated in ARMv6T2 and above.

  • For LDREXD, Rt must be an even numbered register, and not LR.

  • Rt2 must be R(t+1).

  • offset is not permitted.

For Thumb instructions:

  • SP can be used for Rn, but must not be used for Rt or Rt2.

  • For LDREXD, Rt and Rt2 must not be the same register.

  • The value of offset can be any multiple of four in the range 0-1020.


Use LDREX and STREX to implement interprocess communication in multiple-processor and shared-memory systems.

For reasons of performance, keep the number of instructions between corresponding LDREX and STREX instructions to a minimum.

Note The address used in a STREX instruction must be the same as the address in the most recently executed LDREX instruction.


ARM LDREX and STREX are available in ARMv6 and above.

ARM LDREXB, LDREXH, LDREXD, STREXB, STREXD, and STREXH are available in ARMv6K and above.

All these 32-bit Thumb instructions are available in ARMv6T2 and above, except that LDREXD and STREXD are not available in the ARMv7-M architecture.

There are no 16-bit versions of these instructions.


    MOV r1, #0x1                ; load the ‘lock taken’ value
    LDREX r0, [LockAddr]        ; load the lock value
    CMP r0, #0                  ; is the lock free?
    STREXEQ r0, r1, [LockAddr]  ; try and claim the lock
    CMPEQ r0, #0                ; did this succeed?
    BNE try                     ; no – try again
    ....                        ; yes – we have the lock