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LDR (PC-relative)

Load register. The address is an offset from the PC.


LDR{type}{cond}{.W} Rt, label

LDRD{cond} Rt, Rt2, label ; Doubleword



can be any one of:


unsigned Byte (Zero extend to 32 bits on loads.)


signed Byte (LDR only. Sign extend to 32 bits.)


unsigned Halfword (Zero extend to 32 bits on loads.)


signed Halfword (LDR only. Sign extend to 32 bits.)


omitted, for Word.


is an optional condition code.


is an optional instruction width specifier.


is the register to load or store.


is the second register to load or store.


is a PC-relative expression.

label must be within a limited distance of the current instruction.


Equivalent syntaxes are available for the STR instruction in ARM code but they are deprecated in ARMv6T2 and above.

Offset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

The following table shows the possible offsets between the label and the current instruction:

Table 11-11 PC-relative offsets

Instruction Offset range Architectures
ARM LDRD +/– 255 5E
32-bit Thumb LDR, LDRB, LDRSB, LDRH, LDRSH +/– 4095 T2
32-bit Thumb LDRD +/– 1020 T2
16-bit Thumb LDR 0-1020 T

Notes about the Architectures column

Entries in the Architectures column indicate that the instructions are available as follows:


All versions of the ARM architecture.


The ARMv5TE, ARMv6*, and ARMv7 architectures.


The ARMv6T2 and above architectures.


The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

LDR (PC-relative) in Thumb

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb LDR instruction.

Doubleword register restrictions

For 32-bit Thumb instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register.

  • Rt must not be LR.

  • ARM strongly recommends that you do not use R12 for Rt.

  • Rt2 must be R(t + 1).

Use of SP

In ARM code, you can use SP for Rt in LDR word instructions. You can use SP for Rt in LDR non-word ARM instructions but this is deprecated in ARMv6T2 and above.

In Thumb code, you can use SP for Rt in LDR word instructions only. All other uses of SP in these instructions are not permitted in Thumb code.


For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.


In ARMv7-M, LDRD (PC-relative) instructions must be on a word-aligned address.


Must be a multiple of 4.


Rt must be in the range R0-R7. There are no byte, halfword, or doubleword 16-bit instructions.