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Instruction Synchronization Barrier.


ISB{cond} {option}



is an optional condition code.

Note cond is permitted only in Thumb code. This is an unconditional instruction in ARM code.

is an optional limitation on the operation of the hint. The permitted value is:

Full system ISB operation. This is the default and can be omitted.


Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, in addition to all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.

In addition, the ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.

Note When the target architecture is ARMv7-M, you cannot use an ISB instruction in an IT block, unless it is the last instruction in the block.


This ARM and 32-bit Thumb instruction is available in ARMv7.

There is no 16-bit version of this instruction in Thumb.