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3.9. Debug and Trace

The SSE-100 has two configuration options for debug and trace. The system implementer can select either:

  • Cortex-M3 debug and trace capabilities with no requirement for CoreSight SoC.

  • CoreSight SoC compatible configuration which requires CoreSight SoC license. In this case, you must develop your own CoreSight system.

For more information about debug and trace, see the Arm® Cortex®-M3 Processor Technical Reference Manual.

Note

If the system is configured for CoreSight SoC, a license is required for that IP and the related Arm documentation:

  • Arm® CoreSight™ SoC-400 System Design Guide.

  • Arm® CoreSight™ SoC-400 Technical Reference Manual.

  • Arm® CoreSight™ SoC-400 User Guide.

  • Arm® CoreSight™ TPIU-Lite Technical Reference Manual.

  • Arm® CoreSight™ DAP-Lite Technical Reference Manual.