The following figure shows the block diagram for the Cortex-M3 processor logic and CoreSight SoC interface.
The default implementation reuses the TPIU and SWJ-DP from Cortex-M3 package and connects the SWJ-DP and TPIU to the Processor Integration Layer. For basic usage, there is no requirement to license the CoreSight SoC IP.
The system designer can however choose to design a system with the separately licensed CoreSight SoC debug interface connected to the AHB-AP. In this case, the SWJ-DP and TPIU blocks and their corresponding signals are not present.
For more information about the Cortex-M3 processor and the debug and trace logic, see the following documents:
Arm® ARMv7-M Architecture Reference Manual.
Arm® Cortex®-M3 Processor Technical Reference Manual.
Arm® CoreSight™ Components Technical Reference Manual.
Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.
Arm® Embedded Trace Macrocell Architecture Specification.