The SSE-100 infrastructure supports up to four 32KB SRAMs. At least one 32KB SRAM must be implemented (SRAM bank 0).
If a SRAM bank is not implemented and the corresponding MTXREMAP bits are 1, then the corresponding address space is mapped to the AHB Slave expansion port of the interconnect.
In Figure 2.5, the MTXREMAP signals from the configuration logic are static during functional operation.
The SRAM modules are outside of the SSE-100. The subsystem does not implement retention or power-down supports for the SRAMs. It is the responsibility of the SoC integration to implement power domains for the SRAM, control the power modes of the SRAM banks with a SoC level PMU.
The AHB2SRAM bridge always responds with OKAY to all AHB accesses, even if the connected SRAM is not functional because for example it is powered-down or in retention mode.
It is the responsibility of the software to not read or write the SRAMs when they are not functional. If the software tries to access non-accessible SRAM, the AHB2SRAM bridge implementation ensures that system does not go into a deadlock state because of a non-responsive SRAM. Read data is implementation specific.
See also SRAM signals.