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1.2. Compliance

This TRM complements architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards. It does not duplicate information from these sources.

ARM SMMU architecture

The MMU-500 implements the ARM SMMU architecture v2.

See the ARM® System Memory Management Unit Architecture Specification.

ARMv7 and v8 architecture

The MMU-500 supports the ARMv7 and ARMv8 address translation schemes. That is, it supports VMSAv7, VMSAv8-32, and VMSAv8-64, including the long-descriptor and short-descriptor translation table formats.


The 16KB page granule is not supported in the MMU-500.

See the following documents:

  • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

  • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

Low-power interface support

For more information about the MMU-500 low-power interface support, see the following documents:

  • Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces.

  • ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite.