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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

First release


Table C.2. Differences between issue A and issue B
Clarified when a hypervisor is requiredAbout the GIC-400All
Added a note about suitability for use with processors that have requirements on the stability of IRQ and FIQ inputsInterrupt handling and prioritization in the GIC-400All
Clarified what happens to the interrupt input signal for a level-sensitive interrupt in a disabled group when the Distributor is disabledBehavior when the Distributor is disabledAll
Updated bits[15:12] of the Distributor Implementer Identification RegisterTable 3.2Distributor Implementer Identification Register, GICD_IIDRr0p1
Updated bits[15:12] of the CPU Interface Identification RegisterTable 3.6CPU Interface Identification Register, GICC_IIDRr0p1
Updated bits[15:12] of the VM CPU Interface Identification RegisterTable 3.8VM CPU Interface Identification Register, GICV_IIDRr0p1