This appendix describes the technical changes between released issues of this book.
|Clarified when a hypervisor is required||About the GIC-400||All|
|Added a note about suitability for use with processors that have requirements on the stability of IRQ and FIQ inputs||Interrupt handling and prioritization in the GIC-400||All|
|Clarified what happens to the interrupt input signal for a level-sensitive interrupt in a disabled group when the Distributor is disabled||Behavior when the Distributor is disabled||All|
|Updated bits[15:12] of the Distributor Implementer Identification Register||Table 3.2Distributor Implementer Identification Register, GICD_IIDR||r0p1|
|Updated bits[15:12] of the CPU Interface Identification Register||Table 3.6CPU Interface Identification Register, GICC_IIDR||r0p1|
|Updated bits[15:12] of the VM CPU Interface Identification Register||Table 3.8VM CPU Interface Identification Register, GICV_IIDR||r0p1|