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Appendix D. Revisions

This appendix describes the technical changes between released issues of this book.

Table D.1. Differences between issue C and issue D
Cache features updatedCache configurability.r3p0
Note addedAXI master and slave interfaces.All revisions
Write acceptance capability updatedTable 2.3.All revisions
Exclusive cache configuration clarifiedExclusive cache configuration.All revisions
RAM organization updatedRAM organizationr3p0
Figure updatedFigure 2.13r3p0
Cortex-A9 optimizations updatedCortex-A9 optimizationsr3p0
Event pins addedTable 2.21r3p0
Event pin deletedTable 2.21r3p0
Interrupt pin ERRWTINTR description updatedTable 2.22r3p0
Section addedDynamic clock gatingr3p0
Section updatedStandby moder3p0
Example cache controller start-up programming sequence updatedInitialization sequencer3p0
Register map updatedTable 3.1r3p0
Register summary updatedTable 3.2r3p0
Register bit assignments updatedTable 3.3r3p0
Register updatedCache Type Registerr3p0
Register updatedAuxiliary Control Registerr3p0
reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments updatedTable 3.9r3p0
Cache Maintenance Operations table updatedTable 3.15r3p0
Section clarifiedInvalidate OperationsAll revisions
Clock and reset signals updatedTable A.1r3p0
Slave port 0 signals table updatedTable A.3r3p0

Table D.2. Differences between issue D and issue E
Removal of AXI ID encoding tablesMaster and slave port IDsr3p1
Description of a new bit in the Prefetch Control RegisterPrefetch Control Registerr3p1

Table D.3. Differences between issue E and issue F
Hazard checking description clarifiedHazardsr3p1 and r3p2
MBISTDCTL interface signals updatedTable A.9r3p1 and r3p2
Preset offset bit description clarifiedTable 3.39r3p1 and r3p2
CFGBIGEND signal description clarifiedTable A.2r3p1 and r3p2
Bit 25 of reg1_aux_control Register bit assignments Register updatedFigure 3.4r3p1 and r3p2
Speculative read feature clarifiedCortex-A9 optimizationsr3p1 and r3p2
Reset procedure addedReset requirementr3p2

Table D.4. Differences between issue F and issue G
Additional bullet added to note in Double Linefill issuing section. The bullet explains that Double linefills only occur if a WRAP4 or an INCR4 64-bit transaction is received on the slave ports.Double linefill issuingr3p0 to r3p2
Data ram interface behavior clarified.RAM latenciesr3p0 to r3p2
Section added.Tag lock RAMr3p0 to r3p2
Section clarified.AXI exclusive accessesr3p0 to r3p2
DATARDBANKSEL signal description clarified.

Figure 2.8

Figure 2.10

Table A.5

Table B.4

r3p0 to r3p2
Master port behavior table updated.Table 2.19r3p0 to r3p2
Interface signals list updated.Table A.9r3p0 to r3p2
Section updated.Store buffer operationr3p0 to r3p2

Table D.5. Differences between issue G and issue H
Combined acceptance capability attribute clarifiedTable 2.3r3p0 to r3p3
Force write allocate section updatedForce write allocater3p0 to r3p3
Double linefill issuing behavior updated.Double linefill issuingr3p0 to r3p3
Parity and RAM error support behavior updated

Parity and RAM error support

Table 2.23

Table 2.24

Table 2.25

Table 2.26

Table 2.28

r3p0 to r3p3
Cache maintenance operations behavior clarifiedBackground operationsr3p0 to r3p3
Reset sequence updatedReset requirementr3p0 to r3p3