What is the recommended WBUFFER_DEPTH setting on the CoreSight SoC-600 Embedded Trace Router (ETR)?
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Debug and Trace
What is the recommended WBUFFER_DEPTH setting on the CoreSight SoC-600 Embedded Trace Router?
Customer is setting the RTL configuration parameters for the Embedded Trace Router (ETR) that is supplied as part of the CoreSight SoC-600 product.
For optimal ETR AXI performance, Arm recommends configuring the write buffer depth to at least twice the max burst length that is expected to be used in the system. Smaller write buffer sizes, relative to a given burst size, will work, but with reduced AXI utilization.
If the target burst usage is not known, then a good practice is to set the write buffer depth to produce a buffer capacity that is equal to twice the size of the largest cache line in the system. The idea is that SoC memory systems should already be optimized for cache-line-sized bursts. This is, so we can assume that ETR can be programmed to use bursts of that size, and that the memory system will handle it efficiently.
EXAMPLE1: For an Arm processor subsystem with 64-byte cache-line length, then (2 x 64-bytes) corresponds to a 16-entry write buffer for a 64-bit ETR.
EXAMPLE2: For an Arm processor subsystem with 32-byte cache-line length, then (2 x 32-bytes) corresponds to an 8-entry write buffer for a 64-bit ETR.