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Functional description

Table of Contents

About the core
Implementation options
Supported standards and specifications
Test features
Design tasks
Product revisions
Technical overview
About system control
About the Generic Timer
Clocks, resets, and input synchronization
About clocks, resets, and input synchronization
Asynchronous interface
Power management
About power management
Voltage domains
Power domains
Architectural clock gating modes
Core Wait for Interrupt
Core Wait for Event
Power control
Core power modes
Off (emulated)
SIMD dynamic retention
Core dynamic retention
Debug recovery
Encoding for core power modes
Thread power modes
Run mode
Standby mode
Deactivated mode
Relationship between power modes and power domains
Power down sequence
Debug over powerdown
Memory Management Unit
About the MMU
Main functions
AArch64 MMU behavior
TLB organization
IPA cache RAM
Walk cache RAM
TLB match process
Translation table walks
MMU memory accesses
Configuring MMU accesses
Hardware management of the Access flag and dirty state
MMU responses
MMU aborts
External aborts
Mis-programming contiguous hints
Conflict aborts
Memory Behavior
Support for Arm®v8‑A device memory types
Level 1 memory system
About the L1 memory system
Cache behavior
Instruction cache disabled behavior
Instruction cache speculative memory accesses
Data cache disabled behavior
Data cache maintenance considerations
Data cache coherency
Write Streaming Mode
Data cache invalidate on reset
instruction memory system
Program flow prediction
data memory system
Memory system implementation
Internal exclusive monitor
Exclusive monitor
Data prefetching
Direct access to internal memory
Encoding for tag and data in the L1 data cache
Encoding for tag and data in the L1 instruction cache
Encoding for the L2 TLB
Main TLB RAM descriptor fields
Walk cache descriptor fields
IPA cache descriptor fields
Level 2 memory system
About the L2 memory system
Optional integrated L2 cache
Support for memory types
Reliability, Availability, and Serviceability (RAS)
Cache ECC and parity
Cache protection behavior
Uncorrected errors and data poisoning
RAS error types
Error synchronization barrier
Error recording
Error injection
Generic Interrupt Controller CPU interface
About the Generic Interrupt Controller CPU interface
Bypassing the CPU interface
Advanced SIMD and floating-point support
About the Advanced SIMD and floating-point support
Accessing the feature identification registers