Each CPU element contains a single L1 instruction cache that is on the code AHB interface of the Cortex®‑M33 core.
- Reduces the code access fetches targeting the flash memory and therefore reduces activity on the flash and power.
- Reduces the overall latency of code access. This permits increasing the latency of the instruction fetch from memory which might be necessary to deal with long timing paths.
The cache has the following features:
- 2-way set associative.
- 16-Byte cache lines.
- Configurable size. The top-level parameters CPU0_ICACHESIZE and CPU1_ICACHESIZE set the size.
- Configuration interface local to each processor.
- Supports uncached bypass operation.
- The instruction code fetches in the region from
are cached. All accesses to other memory regions are not cached.
- Each cache includes a configuration interface that is only accessible
that is connected to it and it resides at address
. This configuration interface is not accessible to other masters in the system.
The cache supports Secure and Non-secure segregation of contents by retaining the security attributes of the cached contents. If the SAU or the IDAU configurations change, the cache might contain contents that do not match the new security settings. To maintain security, you must therefore disable and invalidate the cache before modifying the SAU or IDAU.
Because this is an instruction cache, only read accesses are subject to caching. All write accesses bypass the cache. If the INVMAT option of the cache is enabled, when a cacheable write access occurs to a line that exists in the cache, that cache line is invalidated.
NoteIf a cache line exists in the cache that matches a non-cacheable write access, the invalidation does not occur. Therefore, when changing the attribute of an address region from cacheable to non-cacheable that the instruction cache accesses, you must invalidate the cache.
The following table lists the instruction cache configuration parameters.
Table 2-3 Instruction cache configurations
|Parameter||Processor 0 configuration||Processor 1 configuration||Processor 0 default value||Processor 1 default value||Description|
Define the cache size. Supported cache sizes:
|DMA||CPU0_ICACHEDMA||CPU1_ICACHEDMA||0||0||Defines the existence of micro DMA capability and line locking capability. When set to 1, the instruction cache provides cache line prefetch and locking capability.|
|INVMAT||CPU0_ICACHEINVMAT||CPU1_ICACHEINVMAT||0||0||Invalidate on Write Match. When set to 1, any cacheable writes to a line that also exists in the instruction cache results in the cache line being invalidated.|
|COFFSET||0||0||0||0||Cacheable Region Offset Upper bits to compare against. This parameter is fixed.|
|COFFSIZE||3||3||3||3||Cacheable Region Size. Value defines the number of upper address bits to compare. Therefore, the addressable space is 2(32-COFFSIZE).|
|STATS||CPU0_ICACHESTATS||CPU1_ICACHESTATS||1||1||1 = include statistics functionality.|
Enable Execute Only Memory support.
When set to 1, the HRUSER signal on the AHB5 Master Expansion Code Interface is used to indicate if current data being returned is Execute Only. If the data type access arriving at the instruction cache targets a XOM location, the instruction cache masks the data.
When set to 0, this HRUSER is ignored by the associated instruction cache.
|REDUCE_READS||ICACHERRDS||1||1||Reduce instruction cache Tag Reads. When set to 1, it masks off an access to the TAG RAM if this set has been previously accessed and the RAM data is valid and does not need re-accessing.|