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VUDOT (vector)

Dot Product vector form with unsigned integers.

Syntax

VUDOT{q}.U8 Dd, Dn, Dm ; 64-bit SIMD vector

VUDOT{q}.U8 Qd, Qn, Qm ; A1 128-bit SIMD vector FP/SIMD registers (A32)

Where:

q
Is an optional instruction width specifier. See Instruction width specifiers.
Dd
Is the 64-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register.
Dm
Is the 64-bit name of the second SIMD and FP source register.
Qd
Is the 128-bit name of the SIMD and FP destination register.
Qn
Is the 128-bit name of the first SIMD and FP source register.
Qm
Is the 128-bit name of the second SIMD and FP source register.

Architectures supported

Supported in Arm®v8.2 and later.

For Armv8.2 and Armv8.3, this is an optional instruction.

Usage

Dot Product vector form with unsigned integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.

Note

ID_ISAR6.DP indicates whether this instruction is supported in the T32 and A32 instruction sets.