is an optional condition code.
Qd, Qn, Qm
specifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dm
specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
is the number of 8-bit elements to extract from the bottom of the second operand vector, in the range 0-7 for doubleword operations, or 0-15 for quadword operations.
VEXT extracts 8-bit elements from the bottom end of the second operand
vector and the top end of the first, concatenates them, and places the result in the
destination vector. See the following figure for an example:
Figure C3-2 Operation of doubleword VEXT for imm = 3
You can specify a datatype of 16, 32, or 64 instead of 8.
In this case,
#imm refers to halfwords, words,
or doublewords instead of referring to bytes, and the permitted
ranges are correspondingly reduced.