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A32/T32 Cryptographic instructions

A set of A32 and T32 cryptographic instructions is available in the Arm®v8 architecture.

These instructions use the 128-bit Advanced SIMD registers and support the acceleration of the following cryptographic and hash algorithms:

  • AES.
  • SHA1.
  • SHA256.

Summary of A32/T32 cryptographic instructions

The following table lists the A32/T32 cryptographic instructions that are supported:

Table C5-1 Summary of A32/T32 cryptographic instructions

Mnemonic Brief description
AESD AES single round decryption
AESE AES single round encryption
AESIMC AES inverse mix columns
AESMC AES mix columns
SHA1C SHA1 hash update (choose)
SHA1H SHA1 fixed rotate
SHA1M SHA1 hash update (majority)
SHA1P SHA1 hash update (parity)
SHA1SU0 SHA1 schedule update 0
SHA1SU1 SHA1 schedule update 1
SHA256H2 SHA256 hash update part 2
SHA256H SHA256 hash update part 1
SHA256SU0 SHA256 schedule update 0
SHA256SU1 SHA256 schedule update 1