Zero extend Halfword.
is an optional condition code.
is the destination register.
is the register holding the value to extend.
is one of:
is rotated right 8 bits.
is rotated right 16 bits.
is rotated right 24 bits.
is omitted, no rotation is performed.
UXTH extends a 16-bit value to a 32-bit value. It does this by:
Rotating the value from
right by 0, 8, 16, or 24 bits.
Extracting bits[15:0] from the value obtained.
Zero extending to 32 bits.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not change the flags.
The following form of this instruction is available in T32 code, and is a 16-bit instruction:
must both be Lo registers.
The 32-bit instruction is available in A32 and T32.
For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.
The 16-bit instruction is available in T32.