is an optional condition code.
is an expression evaluating to an integer in the range:
0 to 224-1 (a 24-bit value) in an A32 instruction.
0-255 (an 8-bit value) in a T32 instruction.
SVC instruction causes an exception.
This means that the processor mode changes to Supervisor, the CPSR
is saved to the Supervisor mode SPSR, and execution branches to
the SVC vector.
imm is ignored by the
processor. However, it can be retrieved by the exception handler
to determine what service is being requested.
SWIin earlier versions of the A32 assembly language.
SWIinstructions disassemble to
SVC, with a comment to say that this was formerly
This instruction does not change the flags.
This instruction is available in A32 and 16-bit T32 and in the Arm®v7 architectures.
There is no 32-bit version of this instruction in T32.