You copied the Doc URL to your clipboard.


Dual 16-bit Signed Multiply with Subtraction of products and 64-bit accumulation.


SMLSD{X}{cond} RdLo, RdHi, Rn, Rm



is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.


is an optional condition code.

RdLo, RdHi

are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand. RdHi and RdLo must be different registers.

Rn, Rm

are the general-purpose registers holding the operands.


SMLSLD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then subtracts the second product from the first, adds the difference to the value in RdLo, RdHi, and stores the result to RdLo, RdHi.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not change the flags.


The 32-bit instruction is available in A32 and T32.

For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.

There is no 16-bit version of this instruction in T32.


    SMLSLD      r3, r0, r5, r1