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Dual 16-bit Signed Multiply with Addition of products and 64-bit Accumulation.


SMLALD{X}{cond} RdLo, RdHi, Rn, Rm



is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.


is an optional condition code.

RdLo, RdHi

are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand. RdHi and RdLo must be different registers.

Rn, Rm

are the general-purpose registers holding the operands.


SMLALD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then adds both products to the value in RdLo, RdHi and stores the sum to RdLo, RdHi.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not change the flags.


The 32-bit instruction is available in A32 and T32.

For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.

There is no 16-bit version of this instruction in T32.


    SMLALD      r10, r11, r5, r1