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Select bytes from each operand according to the state of the APSR GE flags.


SEL{cond} {Rd}, Rn, Rm



is an optional condition code.


is the destination register.


is the register holding the first operand.


is the register holding the second operand.


The SEL instruction selects bytes from Rn or Rm according to the APSR GE flags:

  • If GE[0] is set, Rd[7:0] come from Rn[7:0], otherwise from Rm[7:0].

  • If GE[1] is set, Rd[15:8] come from Rn[15:8], otherwise from Rm[15:8].

  • If GE[2] is set, Rd[23:16] come from Rn[23:16], otherwise from Rm[23:16].

  • If GE[3] is set, Rd[31:24] come from Rn[31:24], otherwise from Rm[31:24].


Use the SEL instruction after one of the signed parallel instructions. You can use this to select maximum or minimum values in multiple byte or halfword data.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not change the flags.


The 32-bit instruction is available in A32 and T32.

For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.

There is no 16-bit version of this instruction in T32.


    SEL     r0, r4, r5
    SELLT   r4, r0, r4

The following instruction sequence sets each byte in R4 equal to the unsigned minimum of the corresponding bytes of R1 and R2:

    USUB8    r4, r1, r2
    SEL      r4, r2, r1