PLD, PLDW, and PLI
Preload Data and Preload Instruction allow the processor to signal the memory system that a data or instruction load from an address is likely in the near future.
can be one of:
Data address with intention to write.
DWif the syntax specifies
is an optional condition code.
is permitted only in T32 code, using a preceding
ITinstruction, but this is deprecated in the Arm®v8 architecture. This is an unconditional instruction in A32 code and you must not use
is the register on which the memory address is based.
is an immediate offset. If offset is omitted, the address is the value in
is a register containing a value to be used as the offset.
is an optional shift.
is a PC-relative expression.
Range of offsets
The offset is applied to the value in
the preload takes place. The result is used as the memory address
for the preload. The range of offsets permitted is:
- -4095 to +4095 for A32 instructions.
- -255 to +4095 for T32 instructions, when
Rnis not PC.
- -4095 to +4095 for T32 instructions, when
The assembler calculates the offset from the PC for you. The assembler generates
an error if
out of range.
Register or shifted register offset
In A32 code, the value in
Rm is added to or
subtracted from the value in
. In T32 code, the value in
can only be added to the value in
. The result is used as the memory address for the preload.
The range of shifts permitted is:
LSL#0 to #3 for T32 instructions.
- Any one of the following for A32 instructions:
LSL#0 to #31.
LSR#1 to #32.
ASR#1 to #32.
ROR#1 to #31.
Address alignment for preloads
No alignment checking is performed for preload instructions.
not be PC. For T32 instructions
must also not be SP.
not be PC for T32 instructions of the syntax
PLD instruction is available in A32.
The 32-bit encoding of
PLD is available in
PLDW is available only in the Armv7 architecture and
above that implement the Multiprocessing Extensions.
PLI is available only in the Armv7 architecture and
There are no 16-bit encodings of these instructions in T32.
These are hint instructions, and their implementation is optional.
If they are not implemented, they execute as