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Load-Acquire Register Exclusive.


This instruction is supported only in Arm®v8.


LDAEX{cond} Rt, [Rn]

LDAEXB{cond} Rt, [Rn]

LDAEXH{cond} Rt, [Rn]

LDAEXD{cond} Rt, Rt2, [Rn]


is an optional condition code.
is the register to load.
is the second register for doubleword loads.
is the register on which the memory address is based.


LDAEX loads data from memory.

  • If the physical address has the Shared TLB attribute, LDAEX tags the physical address as exclusive access for the current processor, and clears any exclusive access tag for this processor for any other physical address.
  • Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.
  • If any loads or stores appear after LDAEX in program order, then all observers are guaranteed to observe the LDAEX before observing the loads and stores. Loads and stores appearing before LDAEX are unaffected.


The PC must not be used for any of Rt, Rt2, or Rn.

For A32 instructions:

  • SP can be used but use of SP for any of Rt, or Rt2 is deprecated.
  • For LDAEXD, Rt must be an even numbered register, and not LR.
  • Rt2 must be R(t+1).

For T32 instructions:

  • SP can be used for Rn, but must not be used for any of Rt, or Rt2.
  • For LDAEXD, Rt and Rt2 must not be the same register.


Use LDAEX and STLEX to implement interprocess communication in multiple-processor and shared-memory systems.

For reasons of performance, keep the number of instructions between corresponding LDAEX and STLEX instructions to a minimum.


The address used in a STLEX instruction must be the same as the address in the most recently executed LDAEX instruction.


These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions.