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Reset signals

The following table shows the reset and reset control signals.

Table A-2 Reset and reset control signals

Signal Direction Description
nCPUPORESET[CN:0] Input

Processor powerup reset:

0

Apply reset to all processor logic.

Processor logic includes Advanced SIMD and floating-point, Debug, ETM trace unit, breakpoint and watchpoint logic.

1Do not apply reset to all processor logic.
nCORERESET[CN:0] Input

Individual core resets excluding Debug and ETM trace unit:

0

Apply reset to processor logic.

Processor logic includes Advanced SIMD and floating-point, but excludes Debug, ETM trace unit, breakpoint and watchpoint logic.

1Do not apply reset to processor logic.
nL2RESET Input

L2 memory system reset:

0Apply reset to shared L2 memory system controller.
1Do not apply reset to shared L2 memory system controller.
L2RSTDISABLE Input

Disable automatic L2 cache invalidate at reset:

0Hardware resets L2 cache.
1Hardware does not reset L2 cache.
WARMRSTREQ[CN:0] Output

Processor Warm reset request:

0Do not apply Warm reset.
1Apply Warm reset.