Developer Tools

AMBA IP-XACT Bus Definitions

The AMBA IP-XACT Bus Definitions describe the AMBA protocols using the IP-XACT (IEEE 1685-2009) format. They describe the interfaces that implement the AMBA protocols. They also provide details for the interface signals, for example signal direction, width, default value, and whether a signal is required or optional.

The bus definitions facilitate the description, exchange, and integration of compatible IP designs. They also facilitate the development of tools for the generation and configuration of IP that implement AMBA interfaces.

Redistribution of the bus definitions is permitted. You can see details in the End User License Agreement included in the bus definitions package.

AMBA TLM Library

The AMBA Transaction-Level Modeling (TLM) Library allows the modeling and simulation of approximately timed (AT) and cycle-accurate (CA) AMBA AXI4 and ACE interfaces.

The AMBA TLM Library is developed in C++ and is provided as a pre-compiled binary library. It is intended for use with:

• Arm Cycle Models
• Custom AT and CA models that are used for virtual prototype development
• Third-party models that use supported AMBA interfaces

AMBA ATP Engine 

The AMBA ATP Engine is a software module that generates synthetic traffic described with the AMBA Adaptive Traffic Profiles (AMBA ATP) specification. The AMBA ATP Engine defines a file format for the input of traffic profiles and exposes an event-driven C/C++ API, for integrating to host platforms. The ATP Engine is platform-independent and can be integrated into different modeling, simulation, and testing tools such as gem5 and verification IPs (VIPs).

AMBA ATP is a synthetic traffic framework and is capable of modeling systems' masters and slaves high-level memory access behavior in a concise, simple, and portable way. Traffic Profiles can be used across multiple tools and design and verification environments to assist with the design and verification of complex SoCs. Among other use cases, they enable a simpler and faster simulation mechanism that is, at the same time, predictable and adaptive.

Protocol Checkers

Protocol Checkers (PCs) observe interface traffic and monitor transactions against a series of protocol rules (assertions). System designers, integrators, and verification engineers can use PCs to confirm that a design complies with the relevant AMBA protocols.

Protocol checkers are written in SystemVerilog Assertion (SVA) and are provided with user guides, which show how to integrate them into a design.