Instruction Set Architecture

An Instruction Set Architecture (ISA) is part of the abstract model of a computer. It defines how software controls the CPU.

The Arm ISA family allows developers to write software and firmware that conforms to the Arm specifications, secure in the knowledge that any Arm-based processor will execute it in the same way. This is the foundation of the Arm portability and compatibility promise, underlying the Arm ecosystem.

Arm Instruction Set Architecture

The Arm architecture supports three instruction sets: A64, A32 and T32.

  • The A64 and A32 instruction sets have fixed instruction lengths of 32-bits.
  • The T32 instruction set was introduced as a supplementary set of 16-bit instructions that supported improved code density for user code. Over time, T32 evolved into a 16-bit and 32-bit mixed-length instruction set. As a result, the compiler can balance performance and code size trade-off in a single instruction set.

Explore these instruction sets:

A64 instruction set

The A64 instruction set, introduced in Armv8-A to support the 64-bit architecture.

Learn more

A32 instruction set

The A32 instruction set, referred to as ‘ARM’ in Armv6 and Armv7 architectures.

Learn more

T32 instruction set

The T32 instruction set, referred to as ‘Thumb’ in Armv6 and Armv7 architectures.

Learn more

Arm Architecture Extensions

Arm provides a number of architecture extensions to address the needs of the next wave of compute. These extensions provide new capabilities for Arm IP.

Custom Instructions

Arm Custom Instructions support the intelligent and rapid development of fully integrated custom CPU instructions without software fragmentation

Learn more

DSP extensions

Arm Cortex processors with digital signal processing (DSP) extensions offer high performance signal processing with flexible, easy-to-use programming

Learn more

Floating Point

The Arm architecture provides high-performance and high-efficiency hardware support for floating-point operations in half-, single-, and double-precision arithmetic

Learn more

Helium

Arm Helium technology is an extension of the Armv8.1-M architecture and delivers a significant performance uplift for machine learning and digital signal processing applications

Learn more

Neon

Arm Neon technology is an advanced Single Instruction Multiple Data (SIMD) architecture extension for the Arm Cortex-A processor series and for Cortex-R52 and Cortex-R82 processors

Learn more

Learning resources

The ISAs commonality and differentiation guide describes some of the features that are specific to each Arm Instruction Set Architecture (ISA) and considers which applications make best use of the ISA features. The focus of the guide is Cortex-R. However, we also consider Cortex-A and Cortex-M, in the context of helping a developer make the right choice for their project.

View the guide

Community Blogs

Blog post image
Relaxed Persist Ordering Using Strand Persistency

Memory consistency models define the ordering of loads and stores to non-overlapping addresses. We explore the more relaxed memory consistency models, and the ordering of persists.

3 months ago by William Wang
Blog post image
Developments in the Arm A-Profile Architecture: Armv8.6-A

The Arm Architecture is continually evolving to meet the needs of our ecosystem partners. This blog gives a high-level overview of some of the changes being introduced in Armv8.6-A. The enhancements to the architecture provide more efficient processi

12 months ago by Nigel Stephens
Blog post image
BFloat16 processing for Neural Networks on Armv8-A

The next revision of the Armv8-A architecture will introduce Neon and SVE vector instruction designed to accelerate Neural Networks using the BFloat16 format.

1 years ago by Nigel Stephens
Blog post image
Introducing high performance device virtualization: Approach to standardiza

In this blog we introduce Arm's approach to accelerators and device virtualization with a view to agreeing standards.

1 years ago by Berenice Mann
Blog post image
The Arm Research Workshop on Novel Algorithms

Arm Research is responsible for delivering a clear vision of disruptive and emerging technologies, and how they may affect our future. This disruptive technology landscape is used to develop our research strategy, which guides internal research,…

1 years ago by Bo Eyole
Blog post image
Architecting a more Secure world with isolation and virtualization

Arm has introduced Secure EL2, which provides mechanisms to isolate secure payloads from each other and from the Normal world. Leveraging this technology requires new thinking in security software architecture for A-Profile processors.

2 years ago by Berenice Mann

Community Forums

Not answered Where do I find presentations and photos from SC'18? 2 votes 4843 views 0 replies Started 1 years ago by John Linford Answer this
Suggested answer problems with timers and i2c
  • Timing
  • Communications Standards
  • STM32 F4
 0 votes 119 views 1 replies Latest yesterday by Andy Neil Answer this
Not answered Does Keil MDK5 support any RTOS with Bluenrg-2?
  • Keil MDK Cortex-M Edition
  • Bluetooth LE
  • CMSIS RTOS
 0 votes 127 views 0 replies Started yesterday by Cletus87408 Answer this
Suggested answer C library folder structure
  • IDEs and Tool Suites
  • Library
 0 votes 176 views 2 replies Latest 2 days ago by Clonimus74 Answer this
Not answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 4843 views
Suggested answer problems with timers and i2c Latest yesterday by Andy Neil 1 replies 119 views
Not answered Does Keil MDK5 support any RTOS with Bluenrg-2? Started yesterday by Cletus87408 0 replies 127 views
Suggested answer C library folder structure Latest 2 days ago by Clonimus74 2 replies 176 views