Instruction Sets

Memory consistency models define the ordering of loads and stores to non-overlapping addresses. We explore the more relaxed memory consistency models, and the ordering of persists.

The Arm Architecture is continually evolving to meet the needs of our ecosystem partners. This blog gives a high-level overview of some of the changes being introduced in Armv8.6-A. The enhancements to the architecture provide more efficient processi

The next revision of the Armv8-A architecture will introduce Neon and SVE vector instruction designed to accelerate Neural Networks using the BFloat16 format.

In this blog we introduce Arm's approach to accelerators and device virtualization with a view to agreeing standards.

Arm Research is responsible for delivering a clear vision of disruptive and emerging technologies, and how they may affect our future. This disruptive technology landscape is used to develop our research strategy, which guides internal research,…

Arm has introduced Secure EL2, which provides mechanisms to isolate secure payloads from each other and from the Normal world. Leveraging this technology requires new thinking in security software architecture for A-Profile processors.